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We have an amazing retention rate, and have recently taken on a number of new staff. Work continues apace, to fix bugs and add new features, both of which take time. Have faith, Onwards! I personally don't expect Serif to be boasting on the forums about amazing progress.
Meh Honest progress is all I look forward to. All the while, being aware this program is still in its 1. Steady progress is better than fast-paced where everything is incompetently built.
I imagine most people's mentality will change at 2. I don't care about version numbers personally. Obviously we'll probably to pay for 2. The question is always: Did you get your moneys worth with 1. If you didn't, wait to see When the 2. OK like many others I need a DAM to work alongside Affinity Photo, at the moment I still use Lightroom 6 perpetual and due to it's age it cannot read my Sony files so I have to go round the houses with the adobe DNG converter, it would be nice to actually no if there is a DAM on the horizon from Serif in the next release of Affinity Photo so I don't go throwing money away on purchasing another app that does have at least a DAM to work from.
I don't actually follow any of the myriad Sportsball enterprises but they could coincide. Affinity Designer 1. I have never mastered color management, period, so I cannot help with that. I would gladly pay for a 2. Affinity Designer were quite cheap and I used it more or less daily. I still don't know how they managed to get enough revenue from v1. But I won't like a subscription plan, of course, I would be furious. Whether it's 1.
I don't think that's the issue. I mean, we don't know what's going on. We think there might be some big changes Or if some problems will finally be solved bounding box, expand stroke and the other I'm kind of joining the grumblers. It's hard to project yourself in a workflow knowing that there are functions that are really missing to be efficient. I'd like to get rid of adobe products I think that paying is not a problem.
But the lack of visibility towards the future of the products. Because in the end we never know what is really planned. Found at www. And as it is it's all very usable, you should only care about 2.
Will be interesting to see what 2. A company cannot charge for a new version of something once purchased, and all "updates" are free. I think both stores expect the software company to make a new product that can be bought fresh or only ever make new software sales to new customers. Quite incredible in my opinion. There is only ever one price for an application on the Mac App Store and the Microsoft Store, so you cannot easily offer a discount code for a new application either.
The software house can choose to leave AppX on the store available to buy after you release "AppX ver2" or not, but neither store has a built-in mechanism for an upgrade process. Biggest software companies in the world and they haven't got this sorted smh.
Patrick Connor Serif Europe Ltd. True nobility lies in being superior to your previous self. Hello I am new to Affinity, and I am wondering why the resolution of the tutorial videos is generally so poor? It makes me wonder is there a minimum size of screen that is needed to be able to use Affinity?
I would have thought that anyone who wanted to buy the apps would still do so, directly from Serif, if that was the only option available. Acer XC : Core i Hexa-core 2. I normally buy software directly from the developer as there are ridiculous fees taken from the app store provider. Serif sell Affinity on the built in OS stores because of market reach and familiarity, but it is always better for Serif to buy direct from us, in that we make more money.
You can buy our software from whichever suits you better and the prices are the same wherever possible. You guys at Serif should talk to the people at Bare Bones Software. See how they first dealt with the Mac App Store and how they deal with it now. With Version 2. Once the proper end-of-life EOL is reached for all Affinity Suite of apps, make noticeable descriptions in the app stores. I think Serif can see from their perspective that they would handle all kinds of transaction, while at the same time they are in complete control of pricing decisions.
There is now no more commission fees to the app stores. Because each of us already has an account, when purchased any Serif products, future upgrade pricings can take into account our previous version purchase. I don't but Software through the Microsoft Store, but if Microsoft and Apple allow to contact Users directly under certain conditions I don't know if that can be arranged.
Since we can attach an acct to the software, it's possible these users can be screened. Maybe there is a way to put the upgrade information on the "open screen" and one-time use token be applied once clicking a banner, etc.
They would end up with a standard upgrade license going forward. I'm sure there's ways I expect all future updates to have been delivered to me from Microsoft Store! You have purchased a license for version 1 of the applications, and all future updates to version 1 of the applications will be delivered via the Microsoft Store and without additional charge. Serif has said that version 2, when it arrives, will require a new purchase. It would not just be an update to your current version 1 applications.
At that point you may purchase the new application from any Store in which Serif decides to sell it. I get everyone is anxious for a big update and the arrival of Publisher for iPad. Me too. Publisher on iPad will make working out of my office so much easier.
I have been waiting for some features to be added for a couple years now that I think would make the suite even more productive for me. That said, Affinity was always open that version 2 would be a paid upgrade. I am more than happy to shell out money for software that works as well as this when they release 2. I have been doing graphics on computers since the 80s and Affinity is one of the best companies I have worked with. I prefer things as they are, they release things when they are ready, not just to get some extra bucks for once a year upgrades if they are ready or not.
I have had some issues over the years and Affinity responded quickly and honestly. It's pretty obvious something is happening and fairly soon. I have work I can accomplish well enough until the new release happens and I'll be excited to see what they have come up with and surprise us with. I don't believe it! It can't be that version 1 and version 2 are offered at the same time.
That would mean that one has an outdated version via Windows Store. A free update to the latest software was always promised at the time of purchase. Moreover, Affinity is not yet a fully developed software. I will definitely not buy a new 2nd Affinity software! It's your loss, have fun paying Adobe instead.
Even with some rough edges the current suite of Affinity apps are more than capable and the price is a steal compared to the competition. The system hardware supports hot-add and hot-remove of this memory region If the Enabled bit is set and the Hot Pluggable bit is clear, the system hardware does not support hot-add or hot-remove of this memory region.
See the corresponding table below for a description of this field. This enables the OSPM to discover the memory that is closest to the ITS, and use that in allocating its management tables and command queue. The Generic Initiator Affinity Structure provides the association between a generic initiator and the proximity domain to which the initiator belongs. Device Handle of the Generic Initiator. Flags - Generic Initiator Affinity Structure. If set, indicates that the Generic Initiator can initiate all transactions at the same architectural level as the host e.
If a generic device with coherent memory is attached to the system, it is recommended to define affinity structures for both the device and memory associated with the device. They both may have the same proximity domain. Supporting a subset of architectural transactions would be only permissible if the lack of the feature does not have material consequences to the memory model.
One example is lack of cache coherency support on the GI, if the GI does not have any local caches to global memory that require invalidation through the data fabric.
OS is assured that the GI adheres to the memory model as the host processor architecture related to observable transactions to memory for memory fences and other synchronization operations issued on either initiator or host. This optional table provides a matrix that describes the relative distance memory latency between all System Localities, which are also referred to as Proximity Domains.
The entry value is a one-byte unsigned integer. Except for the relative distance from a System Locality to itself, each relative distance is stored twice in the matrix. This provides the capability to describe the scenario where the relative distances for the two directions between System Localities is different.
The diagonal elements of the matrix, the relative distances from a System Locality to itself are normalized to a value of The relative distances for the non-diagonal elements are scaled to be relative to For example, if the relative distance from System Locality i to System Locality j is 2. If one locality is unreachable from another, a value of 0xFF is stored in that table entry. Distance values of are reserved and have no meaning. Platforms may contain the ability to detect and correct certain operational errors while maintaining platform function.
These errors may be logged by the platform for the purpose of retrieval. Depending on the underlying hardware support, the means for retrieving corrected platform error information varies. Alternatively, OSPM may poll processors for corrected platform error information. Error log information retrieved from a processor may contain information for all processors within an error reporting group. As such, it may not be necessary for OSPM to poll all processors in the system to retrieve complete error information.
Length, in bytes, of the entire CPET. See corresponding table below. See corresponding table below for details of the Corrected Platform Error Polling Processor structure. If the system maximum topology is not known up front at boot time, then this table is not present. Indicates the maximum number of Proximity Domains ever possible in the system. The number reported in this field is maximum domains - 1.
For example if there are 0x possible domains in the system, this field would report 0xFFFF. Indicates the maximum number of Clock Domains ever possible in the system.
Indicates the maximum Physical Address ever possible in the system. Note: this is the top of the reachable physical address. A list of Proximity Domain Information for this implementation. It is likely that these characteristics may be the same for many proximity domains, but they can vary from one proximity domain to another. This structure optimizes to cover the former case, while allowing the flexibility for the latter as well.
These structures must be organized in ascending order of the proximity domain enumerations. The starting proximity domain for the proximity domain range that this structure is providing information.
The ending proximity domain for the proximity domain range that this structure is providing information. A value of 0 means that the proximity domains do not contain processors. A value of 0 means that the proximity domains do not contain memory. Length in bytes for entire RASF. The Platform populates this field. The Bit Map is described in Section 5. These parameter blocks are used as communication mailbox between the OSPM and the platform, and there is 1 parameter block for each RAS feature.
NOTE: There can be only on parameter block per type. Indicates that the platform supports hardware based patrol scrub of DRAM memory and platform exposes this capability to software using this RASF mechanism. The following table describes the Parameter Blocks. The structure is used to pass parameters for controlling the corresponding RAS Feature. The platform calculates the nearest patrol scrub boundary address from where it can start. This range should be a superset of the Requested Address Range.
The following sequence documents the steps for OSPM to identify whether the platform supports hardware based patrol scrub and invoke commands to request hardware to patrol scrub the specified address range. Identify whether the platform supports hardware based patrol scrub and exposes the support to software by reading the RAS capabilities bitmap in the RASF table.
This table defines the memory power node topology of the configuration, as described earlier in Section 1. The configuration includes specifying memory power nodes and their associated information. Each memory power node is specified using address ranges, supported memory power states. The memory power states will include both hardware controlled and software controlled memory power states.
There can be multiple entries for a given memory power node to support non contiguous address ranges. MPST table also defines the communication mechanism between OSPM and platform runtime firmware for triggering software controlled memory powerstate transitions implemented in platform runtime firmware.
Length in bytes for entire MPST. This field provides information on the memory power nodes present in the system. Further details of this field are specified in Memory Power Node. This field provides information of memory power states supported in the system. The information includes power consumed, transition latencies, relevant flags. See the table below. All other command values are reserved.
The PCC signature. The signature of a subspace is computed by a bitwise-or of the value 0x with the subspace ID. For example, subspace 3 has signature 0x PCC command field: see Section PCC status field: see Section Power State values will be based on the platform capability. A value of all 1s in this field indicates that platform does not implement this field. OSPM should use the ratio of computed memory power consumed to expected average power consumed in determining the memory power management action.
Memory Power State represents the state of a memory power node which maps to a memory address range while the platform is in the G0 working state. It should be noted that active memory power state MPS0 does not preclude memory power management in that state. It only indicates that any active state memory power management in MPS0 is transparent to the OSPM and more importantly does not require assist from OSPM in terms of restricting memory occupancy and activity.
In all three cases, these states require explicit OSPM action to isolate and free the memory address range for the corresponding memory power node. Power state transition diagram is shown in Fig.
If platform is capable of returning to a memory power state on subsequent period of idle, the platform must treat the previously requested memory power state as a persistent hint. This state value maps to active state of memory node Normal operation.
OSPM can access memory during this state. This state value can be mapped to any memory power state depending on the platform capability. By convention, it is required that low value power state will have lower power savings and lower latencies than the higher valued power states. SetMemoryPowerState : The following sequence needs to be done to set a memory power state.
GetMemoryPowerState : The following sequence needs to be done to get the current memory power state. Memory Power Node is a representation of a logical memory region that needs to be transitioned in and out of a memory power state as a unit. This logical memory region is made up of one more system memory address range s. Note that memory power node structure defined in Table 5. This address range should be 4K aligned. If a Memory Power Node contains more than one memory address range i. Memory Power Nodes are not hierarchical.
OSPM is expected to identify the memory power node s that corresponds to the maximum memory address range that OSPM is able to power manage at a given time. The following structure specifies the fields used for communicating memory power node information. Each entry in the MPST table will be having corresponding memory power node structure defined.
This structure communicates address range, number of power states implemented, information about individual power states, number of distinct physical components that comprise this memory power node.
The physical component identifiers can be cross-referenced against the memory topology table entries. The flag describes type of memory node. See the Table 5. This field provides memory power node number. Length in bytes for Memory Power Node Structure. Low 32 bits of Length of the memory range. This field indicates number of power states supported for this memory power node and in turn determines the number of entries in memory power state structure. This field indicates the number of distinct Physical Components that constitute this memory power node.
This field is also used to identify the number of entries of Physical Component Identifier entries present at end of this table. This field provides information of various power states supported in the system for a given memory power node.
This allows system firmware to populate the MPST with a static number of structures but enable them as necessary. This flag indicates that the memory node supports the hot plug feature. See Interaction with Memory Hot Plug. This field provides value of power state. The specific value to be used is system dependent. However convention needs to be maintained where higher numbers indicates deeper power states with higher power savings and higher latencies.
For example, a power state value of 2 will have higher power savings and higher latencies than a power state value of 1. This field provides unique index into the memory power state characteristics entries which will provide details about the power consumed, power state characteristics and transition latencies. The indexing mechanism is to avoid duplication and hence reduce potential for mismatch errors of memory power state characteristics entries across multiple memory nodes.
The table below describes the power consumed, exit latency and the characteristics of the memory power state. This table is referenced by a memory power node. The flag describes the caveats associated with entering the specified power state.
Refer to Table 5. This field provides average power consumed for this memory power node in MPS0 state. This power is measured in milliWatts and signifies the total power consumed by this memory the given power state as measured in DC watts. Note that this value should be used as guideline only for estimating power savings and not as actual power consumed. The actual power consumed is dependent on DIMM type, configuration and memory load. The unit of this field is nanoseconds. If Bit [0] is set, it indicates memory contents will be preserved in the specified power state If Bit [0] is clear, it indicates memory contents will be lost in the specified power state e.
If Bit [1] is set, this field indicates that given memory power state entry transition needs to be triggered explicitly by OSPM by calling the Set Power State command. If Bit [1] is clear, this field indicates that given memory power state entry transition is automatically implemented in hardware and does not require a OSPM trigger. The role of OSPM in this case is to ensure that the corresponding memory region is idled from a software standpoint to facilitate entry to the state.
Not meaningful for MPS0 - write it for this table. If Bit [1] is set, this field indicates that given memory power state exit needs to be explicitly triggered by the OSPM before the memory can be accessed. System behavior is undefined if OSPM or other software agents attempt to access memory that is currently in a low power state. If Bit [1] is clear, this field indicates that given memory power state is exited automatically on access to the memory address range corresponding to the memory power node.
Exit Latency provided in the Memory Power Characteristics structure for a specific power state is inclusive of the entry latency for that state. Not all memory power management states require OSPM to actively transition a memory power node in and out of the memory power state. Platforms may implement memory power states that are fully handled in hardware in terms of entry and exit transition.
In such fully autonomous states, the decision to enter the state is made by hardware based on the utilization of the corresponding memory region and the decision to exit the memory power state is initiated in response to a memory access targeted to the corresponding memory region.
The role of OSPM software in handling such autonomous memory power states is to vacate the use of such memory regions when possible in order to allow hardware to effectively save power.
No other OSPM initiated action is required for supporting these autonomously power managed regions. However, it is not an error for OSPM explicitly initiates a state transition to an autonomous entry memory power state through the MPST command interface.
The platform may accept the command and enter the state immediately in which case it must return command completion with SUCCESS b status. Platform firmware may have regions of memory reserved for its own use that are unavailable to OSPM for allocation. Memory nodes where all or a portion of the memory is reserved by platform firmware may pose a problem for OSPM because it does not know whether the platform firmware reserved memory is in use.
If the platform firmware reserved memory impacts the ability of the memory power node to enter memory power state s , the platform must indicate to OSPM by clearing the Power Managed Flag - see Table 5. This allows OSPM to ignore such ranges from its memory power optimization.
The memory power state table describes address range for each of the memory power nodes specified. An example of policy which can be implemented in OSPM for memory coalescing is: OSPM can prefer allocating memory from local memory power nodes before going to remote memory power nodes. The later sections provide sample NUMA configurations and explain the policy for various memory power nodes. The hot pluggable memory regions are described using memory device objects see Section 9.
The memory power state table MPST is a static structure created for all memory objects independent of hot plug status online or offline during initialization. The association between memory device object e. It is recommended that the OSes if possible allocate this memory from memory ranges corresponding to memory power nodes that indicate they are not power manageable. This allows OS to optimize the power manageable memory power nodes for optimal power savings.
OSes can assume that memory ranges that belong to memory power nodes that are power manageable as indicated by the flag are interleaved in a manner that does no impact the ability of that range to enter power managed states. For example, such memory is not cacheline interleaved. Reference to memory in this document always refers to host physical memory.
For virtualized environments, this requires hypervisors to be responsible for memory power management. Hypervisors also have the ability to create opportunities for memory power management by vacating appropriate host physical memory through remapping guest physical memory. This table describes the memory topology of the system to OSPM, where the memory topology can be logical or physical.
The topology is provided as a hierarchy of memory devices where the top level memory devices e. DIMMs associated with a parent memory device. The number of top level Memory Device structures that immediately follow. A zero in this field indicates no Memory Device structures follow. A list of memory device structures for the platform. Length in bytes for this structure.
The length includes the Type Specific Data, but not memory devices associated with this device. The number of Memory Devices associated with this device. Type specific data. Interpretation of this data is specific to the type of the memory device. It is not expected that OSPM will utilize this field.
The Boot Graphics Resource Table BGRT is an optional table that provides a mechanism to indicate that an image was drawn on the screen during boot, and some information about the image.
The table is written when the image is drawn on the screen. This should be done after it is expected that any firmware components that may write to the screen are done doing so and it is known that the image is the only thing on the screen. If the boot path is interrupted e. A 4-byte bit unsigned long describing the display X-offset of the boot image. X, Y display offset of the top left corner of the boot image.
The top left corner of the display is at offset 0, 0. A 4-byte bit unsigned long describing the display Y-offset of the boot image.
The version field identifies which revision of the BGRT table is implemented. The version field should be set to 1. The Image type field contains information about the format of the image being returned. If the value is 0, the Image Type is Bitmap. The Image Address contains the location in memory where an in-memory copy of the boot image can be found.
The image should be stored in EfiBootServicesData, allowing the system to reclaim the memory when the image is no longer needed. The Image Offset contains 2 consecutive 4 byte unsigned longs describing the X, Y display offset of the top left corner of the boot image. This section describes the format of the Firmware Performance Data Table FPDT , which provides sufficient information to describe the platform initialization performance records.
This information represents the boot performance data relating to specific tasks within the firmware boot process. The FPDT includes only those mileposts that are part of every platform boot process:. End of reset sequence Timer value noted at beginning of platform boot firmware initialization - typically at reset vector. All timer values are express in 1 nanosecond increments.
For example, if a record indicates an event occurred at a timer value of , this means that For the Firmware Performance Data Table conforming to this revision of the specification, the revision is 1.
A performance record is comprised of a sub-header including a record type and length, and a set of data. The format of the data is specific to the record type. In this manner, records are only as large as needed to contain the specific type of data to be conveyed. Note that unless otherwise specified, multiple records are permitted for a given type, because some events may occur multiple times during the boot process. This value is updated if the format of the record type is extended.
Any changes to a performance record layout must be backwards-compatible in that all previously defined fields must be maintained if still applicable, but newly defined fields allow the length of the performance record to be increased. Previously defined record fields must not be redefined, but are permitted to be deprecated.
The table below describes the various Runtime Performance records and their corresponding Record Types. Performance record showing basic performance metrics for critical phases of the firmware boot process.
The record pointer is a required entry in the FPDT for any system, and the pointer must point to a valid static physical address. Only one of these records will be produced. The record pointer is a required entry in the FPDT for any system supporting the S3 state, and the pointer must point to a valid static physical address.
It includes a header, defined in Table 5. All event entries will be overwritten during the platform runtime firmware S4 resume sequence. Other entries are optional. This includes the header and allocated size of the subsequent records. The Firmware Basic Boot Performance Data Record contains timer information associated with final OS loader activity, as well as data associated with boot time starting and ending information.
Timer value logged at the beginning of firmware image execution. This may not always be zero or near zero. Timer value logged just prior to loading the OS boot loader into memory. For non-UEFI compatible boots, this field must be zero. Timer value logged just prior to launching the currently loaded OS boot loader image. All event entries must be initialized to zero during the initial boot sequence, and overwritten during the platform runtime firmware S3 resume sequence.
Length of the S3 Performance Table. This size would at minimum include the size of the header and the Basic S3 Resume Performance Record. Timer recorded at the end of platform runtime firmware S3 resume, just prior to handoff to the OS waking vector. Average timer value of all resume cycles logged since the last full boot sequence, including the most recent resume.
Note that the entire log of timer values does not need to be retained in order to calculate this average. The bit physical address at which the Counter Control block is located. This value is optional if the system implements EL3 Security Extensions.
This value is optional, as an operating system executing in the non-secure world EL2 or EL1 , will ignore the content of these fields. Flags for the secure EL1 timer defined below. This value is optional, as an operating system executing in the non-secure world EL2 or EL1 will ignore the content of this field. The bit physical address at which the Counter Read block is located.
This field is mandatory for systems implementing ARMv8. For systems not implementing ARMv8. Flags for the virtual EL2 timer defined below. Array of Platform Timer Type structures describing memory-mapped Timers available on this platform.
These structures are described in the sections below. These timers are in addition to the per-processor timers described above them in the GTDT. The first byte of each structure declares the type of that structure and the second and third bytes declare the length of that structure. The GT Block is a standard timer block that is mapped into the system address space. Flags for the GTx physical timer. Flags for the GTx virtual timer, if implemented.
Interleave Structure s see Section 5. Flush Hint Address Structure s see Section 5. Platform Capabilities Structure see Section 5. The following figure illustrates the above structures and how they are associated with each other. This allows OSPM to ignore unrecognized types. Platform is allowed to implement this structure just to describe system physical address ranges that describe Virtual CD and Virtual Disk.
Value of 0 is Reserved and shall not be used as an index. Integer that represents the proximity domain to which the memory belongs. This number must match with corresponding entry in the SRAT table. Opaque cookie value set by platform firmware for OSPM use, to detect changes that may impact the readability of the data. Refer to the UEFI specification for details. Handle i. There could be multiple regions within the device corresponding to different address types.
Also, for a given address type, there could be multiple regions due to interleave discontinuity. Typically, only block region requires the interleave structure since software has to undo the effect of interleave.
This structure describes the memory interleave for a given address range. Since interleave is a repeating pattern, this structure only describes the lines involved in the memory interleave before the pattern start to repeat. Index must be non-zero. Line SPA is naturally aligned to the Line size. Length in bytes for entire structure. The length of this structure is either 32 bytes or 80 bytes. The length of the structure can be 32 bytes only if the Number of Block Control Windows field has a value of 0.
Byte 1 of this field is reserved. Identifier for the NVDIMM non-volatile memory subsystem controller, assigned by the non-volatile memory subsystem controller vendor. Revision of the NVDIMM non-volatile memory subsystem controller, assigned by the non-volatile memory subsystem controller vendor.
SPD byte Validity of this field is indicated in Valid Fields Bit [0]. Fields that follow this field are valid only if the number of Block Control Windows is non-zero. In Bytes. Logical offset. Refer to Note. Logical offset in bytes.
Refer to Note1. Bit [0] set to 1 to indicate that the Block Data Windows implementation is buffered. The content of the data window is only valid when so indicated by Status Register. The logical offset is with respect to the device, not with respect to system physical address space. Software should construct the device address space accounting for interleave before applying the block control start offset.
Logical offset in bytes see note below. The address of the next block is obtained by adding the value of this field to Size of Block Data Window. The logical offset is with respect to the device not with respect to system physical address space. Software should construct the device address space accounting for interleave before applying the Block Data Window start offset. Software needs an assurance of durability i. Note that the platform buffers do not include processor cache s!
Processors typically include ISA to flush data out of processor caches. Software is allowed to write up to a cache line of data. The content of the data is not relevant to the functioning of the flush hint mechanism.
The bit index of the highest valid capability implemented by the platform. The subsequent bits shall not be considered to determine the capabilities supported by the platform. This format matches the order of SPD bytes to from low to high i. The table is applicable to systems where a secure OS partition and a non-secure OS partition co-exist.
A secure device is a device that is protected by the secure OS, preventing accesses from non-secure OS. The table provides a hint as to which devices should be protected by the secure OS. The enforcement of the table is provided by the secure OS and any pre-boot environment preceding it. The table itself does not provide any security guarantees. It is the responsibility of the system manufacturer to ensure that the operating system is configured to enable security features that make use of the SDEV table.
Device is listed in SDEV. This provides a hint that the device should be always protected within the secure OS. For example, the secure OS may require that a device used for user authentication must be protected to guard against tampering by malicious software.
This provides a hint that the device should be initially protected by the secure OS, but it is up to the discretion of the secure OS to allow the device to be handed off to the non-secure OS when requested. Any OS component that expected the device to be operating in secure mode would not correctly function after the handoff has been completed. For example, a device may be used for variety of purposes, including user authentication.
If the secure OS determines that the necessary components for driving the device are missing, it may release control of the device to the non-secure OS.
In this case, the device cannot be used for secure authentication, but other operations can correctly function. Device not listed in SDEV. For example, the status quo is that no hints are provided. Any OS component that expected the device to be in secure mode would not correctly function.
Reserved for future use. For forward compatibility, software skips structures it does not comprehend by skipping the appropriate number of bytes indicated by the Length field.
All new device structures must include the Type, Flags, and Length fields as the first 3 fields respectively.
Length of the list of Secure Access Components data. Identification Based Secure Access Component. A minimum of one is required for a secure device. When there are multiple Identification Components present, priority is determined by list order.
Memory Based Secure Access Component. For forward compatibility, software skips structures that it does not comprehend by skipping the appropriate number of bytes indicated by the Length field.
All new device structures must include the Type, Flags, and Length fields as the first 3 fields, respectively. Even numbered offsets contain the Device numbers, and odd numbered offsets contain the Function numbers.
Each subsequent pair resides on the bus directly behind the bus of the device identified by the previous pair. The software is expected to use this information as a hint for optimization, or when the system has heterogeneous memory.
Memory Proximity Domain Attributes Structure s. Describes attributes of memory proximity domains. Describes the memory access latency and bandwidth information from various memory access initiator proximity domains. The optional access mode and transfer size parameters indicate the conditions under which the Latency and Bandwidth are achieved. Memory Side Cache Information Structure s. Describes memory side cache information for memory proximity domains if the memory side cache is present and the physical device SMBIOS handle forms the memory side cache.
Memory side cache allows to optimize the performance of memory subsystems. When the software accesses an SPA, if it is present in the near memory hit it would be returned to the software, if it is not present in the near memory miss it would access the next level of memory and so on. The Level n Memory acts as memory side cache to Level n-1 Memory and Level n-1 memory acts as memory side cache for Level n-2 memory and so on.
If Non-Volatile memory is cached by memory side cache, then platform is responsible for persisting the modified contents of the memory side cache corresponding to the Non-Volatile memory area on power failure, system crash or other faults. This structure describes the system physical address SPA range occupied by the memory subsystem and its associativity with processor proximity domain as well as hint for memory usage. Bit [0]: set to 1 to indicate that data in the Proximity Domain for the Attached Initiator field is valid.
Bit [1]: Reserved. Previously defined as Memory Proximity Domain field is valid. Deprecated since ACPI 6. Bit [2]: Reserved. Previously defined as Reservation Hint. Bits [] : Reserved. This field is valid only if the memory controller responsible for satisfying the access to memory belonging to the specified memory proximity domain is directly attached to an initiator that belongs to a proximity domain.
In that case, this field contains the integer that represents the proximity domain to which the initiator Generic Initiator or Processor belongs. Note: this field provides additional information as to the initiator node that is closest as in directly attached to the memory address ranges within the specified memory proximity domain, and therefore should provide the best performance.
Previously defined as the Range Length of the region in bytes. The Entry Base Unit for latency is in picoseconds. The Initiator to Target Proximity Domain matrix entry can have one of the following values:. The lowest latency number represents best performance and the highest bandwidth number represents best performance. The latency and bandwidth numbers represented in this structure correspond to specification rated latency and bandwidth for the platform.
The represented latency is determined by aggregating the specification rated latencies of the memory device and the interconnects from initiator to target. The represented bandwidth is determined by the lowest bandwidth among the specification rated bandwidth of the memory device and the interconnects from the initiator to target.
Multiple table entries may be present, based on qualifying parameters, like minimum transfer size, etc. They may be ordered starting from most- to least-optimal performance. Unless specified otherwise in the table, the reported numbers assume naturally aligned data and sequential access transfers. Indicates total number of Proximity Domains that can initiate memory access requests to other proximity domains.
Indicates total number of Proximity Domains that can act as target. This is typically the Memory Proximity Domains. Base unit for Matrix Entry Values latency or bandwidth. Base unit for latency in picoseconds.
This field shall be non-zero. The Flag field in this table allows read latency, write latency, read bandwidth and write bandwidth as well as Memory Hierarchy levels, minimum transfer size and access attributes.
Hence this structure could be repeated several times, to express all the appropriate combinations of Memory Hierarchy levels, memory and transfer attributes expressed for each level. If multiple structures are present, they may be ordered starting from most- to least-optimal performance.
If either latency or bandwidth information is being presented in the HMAT, it is required to be complete with respect to initiator-target pair entries. For example, if read latencies are being included in the SLLBI, then read latencies for all initiator-target pairs must be present. If some pairs are incalculable, then the read latency dataset must be omitted entirely.
It is acceptable to provide only a subset of the possible datasets. For example, it is acceptable to provide read latencies but omit write latencies. This provides OSPM a complete picture for at least one set of attributes, and it has the choice of keeping that data or discarding it. System memory hierarchy could be constructed to have a large size of low performance far memory and smaller size of high performance near memory.
The Memory Side Cache Information Structure describes memory side cache information for a given memory domain. The software could use this information to effectively place the data in memory to maximize the performance of the system memory that use the memory side cache. Integer that represents the memory proximity domain to which the memory side cache information applies. Implementation Note: A proximity domain should contain only one set of memory attributes.
If memory attributes differ, represent them in different proximity domains. If the Memory Side Cache Information Structure is present, the System Locality Latency and Bandwidth Information Structure shall contain latency and bandwidth information for each memory side cache level. This is intended as a standard mechanism for the OSPM to notify the platform of a fatal crash e. This table is intended for platforms that provide debug hardware facilities that can capture system info beyond the normal OS crash dump.
This trigger could be used to capture platform specific state information e. This type of debug feature could be leveraged on mobile, client, and enterprise platforms.
Certain platforms may have multiple debug subsystems that must be triggered individually. This table accommodates such systems by allowing multiple triggers to be listed. Please refer to Section 5. Other platforms may allow the debug trigger for capture system state to debug run-time behavioral issues e.
When multiple triggers exist, the triggers within each of the two groups, defined by trigger order, will be executed in order. Note: The mechanism by which this system debug state information is retrieved by the user is platform and vendor specific.
This will most likely will require special tools and privileges in order to access and parse the platform debug information captured by this trigger. It also describes per trigger flags. Each Identifier is 2 bytes. Must provide a minimum of one identifier. Used in fatal crash scenarios: 0: OSPM must initiate trigger before kernel crash dump processing 1: OSPM must initiate trigger at the end of crash dump processing.
A platform debug trigger can choose to use any type of PCC subspace. The definition of the shared memory region for a debug trigger will follow the definition of shared memory region associated with the PCC subspace type used for the debug trigger. For example if a platform debug trigger chooses to use Generic PCC communication subspace Type 0 , then it will use the Generic Communication Channel shared memory region described in Section If a platform debug trigger choose to use a PCC communication subchannel that uses a Generic Communication shared memory region then it will write the debug trigger command in the command field.
The platform can also use the PCC sub channel Type 5 for debug a trigger. A platform debug trigger using PCC Communication sub channel Type 5 will use the shared memory region to share vendor-specific debug information. The following table defines the Type-5 PCC channel shared memory region definition for debug trigger. For example, subspace 3 has the signature 0x Vendor specific area to share additional information between OSPM and platform. The length of the vendor specified area must be 4 bytes less than the Length field specified in the PCCT entry referring to this shared memory space.
PCC command field, see Section 14 and Table 5. PCC status field see Section Trigger Order 1: Triggers are invoked by OSPM at the end of crash dump processing functions, typically after the kernel has processed crash dumps. Capturing platform specific debug information from certain IPs would require intrusive mechanism which may limit kernel operations after the operations.
Trigger order allows the platform to define such operations that will be invoked at the end of kernel operations by OSPM. To illustrate how these debug triggers are intended to be used by the OS, consider this example of a system with 4 independent debug triggers as shown in Fig. Note: This example assumes no vendor specific communication is required, so only PCC command 0x0 is used. When the OS encounters a fatal crash, prior to collecting a crash dump and rebooting the system, the OS may choose to invoke the debug triggers in the order listed in the PDTT.
Describing the 4 triggers illustrated in Fig. Since OS must wait for completion, OS must write PCC command 0x0 and write to the doorbell register per section 14 and poll for the completion bit. When wait for completion is necessary, the OS must poll bit zero completion bit of the status field of that PCC channel see Table This optional table is used to describe the topological structure of processors controlled by the OSPM, and their shared resources, such as caches.
The table can also describe additional information such as which nodes in the processor topology constitute a physical package.
The processor hierarchy node structure is described in Table 5. This structure can be used to describe a single processor or a group. To describe topological relationships, each processor hierarchy node structure can point to a parent processor hierarchy node structure.
This allows representing tree like topology structures. Multiple trees may be described, covering for example multiple packages. For the root of a tree, the parent pointer should be 0. If PPTT is present, one instance of this structure must be present for every individual processor presented through the MADT interrupt controller structures.
In addition, an individual entry must be present for every instance of a group of processors that shares a common resource described in the PPTT. Each physical package in the system must also be represented by a processor node structure.
Each processor node includes a list of resources that are private to that node. For example, an SoC level processor node might contain two references, one pointing to a Level 3 cache resource and another pointing to an ID structure. For compactness, separate instances of an identical resource can be represented with a single structure that is listed as a resource of multiple processor nodes.
For example, is expected that in the common case all processors will have identical L1 caches. For these platforms a single L1 cache structure could be listed by all processors, as shown in the following figure. Note: though less space efficient, it is also acceptable to declare a node for each instance of a resource.
In the example above, it would be legal to declare an L1 for each processor. Note: Compaction of identical resources must be avoided if an implementation requires any resource instance to be referenced uniquely.
For example, in the above example, the L1 resource of each processor must be declared using a dedicated structure to permit unique references to it. Reference to parent processor hierarchy node structure. The reference is encoded as the difference between the start of the PPTT table and the start of the parent processor structure entry.
A value of zero must be used where a node has no parent. If the processor structure represents a group of associated processors, the structure might match a processor container in the name space.
Where there is a match it must be represented. Each resource is a reference to another PPTT structure. The structure referred to must not be a processor hierarchy node. Each resource structure pointed to represents resources that are private the processor hierarchy node. For example, for cache resources, the cache type structure represents caches that are private to the instance of processor topology represented by this processor hierarchy node structure.
The references are encoded as the difference between the start of the PPTT table and the start of the resource structure entry. Set to 1 if this node of the processor topology represents the boundary of a physical package, whether socketed or surface mounted. Set to 0 if this instance of the processor topology does not represent the boundary of a physical package. Each valid processor must belong to exactly one package. That is, the leaf must itself be a physical package or have an ancestor marked as a physical package.
For leaf entries: must be set to 1 if the processing element representing this processor shares functional units with sibling nodes. For non-leaf entries: must be set to 0. A value of 1 indicates that all children processors share an identical implementation revision. This field should be ignored on leaf nodes by the OSPM. Note: this implies an identical processor version and identical implementation reversion, not just a matching architecture revision. Threads sharing a core must be grouped under a unique Processor hierarchy node structure for each group of threads.
Processors may be marked as disabled in the MADT. In this case, the corresponding processor hierarchy node structures in PPTT should be considered as disabled. Additionally, all processor hierarchy node structures representing a group of processors with all child processors disabled should be considered as being disabled.
All resources attached to disabled processor hierarchy node structures in PPTT should also be considered disabled. The cache type structure is described in Table 5. The cache type structure can be used to represent a set of caches that are private to a particular processor hierarchy node structure, that is, to a particular node in the processor topology tree.
The set of caches is described as a NULL, or zero, terminated linked list. Only the head of the list needs to be listed as a resource by a processor node and counted toward Number of Private Resources , as the cache node itself contains a link to the next level of cache.
Cache type structures are optional, and can be used to complement or replace cache discovery mechanisms provided by the processor architecture. For example, some processor architectures describe individual cache properties, but do not provide ways of discovering which processors share a particular cache. When cache structures are provided, all processor caches must be described in a cache type structure.
Each cache type structure includes a reference to the cache type structure that represents the next level cache. The list must include all caches that are private to a processor hierarchy node.
It is not permissible to skip levels. That is, a cache node included in a given hierarchy processor node level must not point to a cache structure referred to by a processor node in a different level of the hierarcy.
Processors, or higher level nodes within the hierarchy, with separate instruction and data caches must describe the instruction and data caches with separate linked lists of cache type structures both listed as private resources of the relevant processor hierarchy node structure. If the separate instruction are data caches are unified at a higher level of cache then the linked lists should converge. Each processor has private L1 data, L1 intruction and L2 caches.
The two processors are contained in a cluster which provides an L3 cache. The resulting list denotes all private caches at the processor level. The L3 node in turn has no next level of cache. An entry in the list indicates primarily that a cache exists at this node in the hierarchy.
Where possible, cache properties should be discovered using processor architectural mechanisms, but the cache type structure may also provide the properties of the cache. A flag is provided to indicate whether properties provided in the table are valid, in which case the table content should be used in preference to processor architected discovery.
On Arm-based systems, all cache properties must be provided in the table. Reference to next level of cache that is private to the processor topology instance. The reference is encoded as the difference between the start of the PPTT table and the start of the cache type structure entry. This value will be zero if this entry represents the last cache level appropriate to the the processor hierarchy node structures using this entry.
Unique, non-zero identifier for this cache. If Cache ID is valid as indicated by the Flags field, then this structure defines a unique cache in the system. Set to 1 if the size properties described is valid.
A value of 0 indicates that, where possible, processor architecture specific discovery mechanisms should be used to ascertain the value of this property. Set to 1 if the number of sets property described is valid.
Set to 1 if the associativity property described is valid. Set to 1 if the allocation type attribute described is valid. A value of 0 indicates that, where possible, processor architecture specific discovery mechanisms should be used to ascertain the value of this attribute. Set to 1 if the cache type attribute described is valid.
Set to 1 if the write policy attribute described is valid. Set to 1 if the line size property described is valid. Set to 1 if the Cache ID property described is valid. This section describes the format of the Platform Health Assessment Table PHAT , which provides a means by which a platform can expose an extensible set of platform health related telemetry that may be useful for software running within the constraints of an operating system. These elements are typically going to encompass things that are likely otherwise not enumerable during the OS runtime phase of operations, such as version of pre-OS components, or health status of firmware drivers that were executed by the platform prior to launch of the OS.
It is not expected that the OSPM would act on the data being exposed. For the PHAT confirming to this revision of the specification, the revision is 1. A platform health assessment record is comprised of a sub-header including a record type and length, and a set of data. The format of the record layout is specific to the record type. Any changes to a platform health assessment record layout must be backwards compatible in that all previously defined fields must be maintained if still applicable, but newly defined fields allow the length of the platform health record to be increased.
Note that unless otherwise specified, multiple platform telemetry records are permitted in the PHAT for a given type. Pre-OS platform health assessment record containing version data for components within the platform firmware, option ROMs, and other pre-OS platform components. Pre-OS platform health assessment record containing health-related information for pre-OS platform components. A platform health assessment record which contains the version-related information associated with pre-OS components in the platform.
A platform health assessment record which contains the health-related information associated with pre-OS components in the platform. This structure is intended to be used to identify the barebones state of a pre-OS component in a generic fashion.
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